1. Field of the Invention
The present invention relates to semiconductor memories, and more specifically to dual-ported memories including a memory array capable of being accessed randomly and a serial access register capable of serial data transfer to and from the memory. The dual-ported two-dimensional memory of this type is commonly referred to as a video RAM.
2. Background of the Invention
A dual-ported memory of the type discussed in this application is used, for example, for storing picture data to be input to a cathode ray tube. The picture data is randomly accessed to write or update the image in memory and then subsequently accessed serially to generate the image on the cathode ray tube. A memory of this type can store images captured by a video camera or other scanning device or it may be used to store images generated by a graphics ordering processing system.
The image to be displayed is divided into a number of discrete picture elements or pixels. Each pixel represents a physical position on the output display device and can have associated with it a color or specific shade of gray. In image and graphics systems the pixels of a display are each represented by a value stored in a memory device. This memory representation of a display is typically referred to as a frame buffer. A high resolution display, such as the IBM 5080 Graphics System, typically has an image of 1024.times.1024 or 1,048,576 pixels. Each pixel value can be represented by 1 to 24 or more bits thus requiring a large amount of memory to store the image. This requirement for large amounts of high speed memory (even by modern standards) leads to the use of the highest density memory parts available for graphic system devices. Typically, Dynamic Random Access Memories ("DRAMs") provide the highest memory density. The nature of video display scan patterns and update rates points to a need for even faster access times and a need to decouple the updating of the frame buffer from the scanning out of the stored values (through video generation circuitry) for display on a video monitor.
Video RAMs are a specialized form of Dynamic RAM memory. They are designed to solve the problem of simultaneously displaying the contents of a graphics frame buffer to the screen while allowing the graphics or image processor to update the frame buffer with new data. Video RAMs contain two Input/Output ports (one for random access and one for serial access) and one address port. These memories are frequently referred to as dual-port memories. In addition to the standard DRAM random access array of rows and columns, a Serial Access Memory ("SAM") register has been added to support serial input and output.
Video RAMs of this type are known in the prior art, for example U.S. Pat. No. 4,541,075 to Dill et al. describes such a memory device. The graphics or image processor updates the frame buffer by writing into the random access array. The serial access memory (SAM) register is designed to sequentially shift the contents of its buffer to the display independently of the random access array. The only time the random array and the SAM do not operate independently is when the SAM needs to be loaded with new data from the random array. The SAM is loaded by executing a special memory cycle called a Read Data Transfer which copies an entire row of the random array into the SAM. External controls allow the data to be sequentially clocked out of the SAM into circuitry which updates the video monitor. The clock rate of the SAM is typically between 3-4 times faster than a standard random access cycle.
Second generation VRAMs were enhanced with the ability to transfer half a row of random access memory into half of the SAM while the other half of the SAM is being scanned out to the display. This is known as a split row transfer. An output status pin known as QSF is typically provided to indicate the half of the SAM being scanned out.
Split row transfer solves the problems of close timing tolerances between the serial access memory and the Read Data Transfer process used to load the SAM. When a standard Read Data Transfer is done, a whole row is copied from the random array to the SAM. If this is done while the Serial Clock ("SC") is scanning data out of the SAM there are close timing requirements between the Data Transfer ("DT") pin and the SC pin to guarantee the desired switching point from old row data to new row data. Because of the speed of the Serial Clock and the asynchronous (independent) nature of the SAM, the proper control of the DT pin is difficult. Split row transfers are designed to solve this problem. While the serial clock is scanning out data from the low half of the SAM, a split row data transfer can occur in the upper half of the SAM and vice versa. The close timing coordination between SC and DT is no longer required. The operation between the SAM and the random array is almost completely decoupled.
During both a Read Data Transfer and a Split Read Data Transfer the row address selects the row (or part row) to transfer to the SAM. The column address is used as a starting address pointer, or tap pointer, in the SAM. This address indicates where the SAM will begin scanning out data. For Split Row Transfers, the second half of the SAM has a separate tap address. Present VRAMs start shifting out of the SAM at the tap address and switch to shifting out of the second half of the SAM only when the half SAM boundary is reached. The use of the tap addresses is described in the prior art, for example U.S. Pat. No. 4,825,411.
Split row transfer is a step toward decoupling the timing of the random access of the VRAM from the timing of the serial side of the VRAM. Present split row transfer mechanisms provide for selecting the starting point for shifting out data, but do not provide a means for selecting when to stop shifting out of one half of the SAM and begin shifting out of the other half of the SAM. For frame buffer organizations that break a VRAM row into multiple scan lines of the display, the utility of the Split Row Transfer is nullified. The only way to scan out only a part of the SAM after the starting address is to do a Read Data Transfer with the new row of data. The timing restrictions of DT and SC are then in effect. To make effective use of Split Row Transfer, a mechanism must exist to select the point at which the scanning of the SAM switches halves and begins at the second tap address. It is an object of the present invention to provide an ability to select this register switching point.